The present invention relates to a semiconductor device with its isolation film and source/drain contacts self-aligned with its gate electrode and a method for fabricating a device with such a structure.
Recently, the number of semiconductor devices that can be integrated on a single chip has increased by leaps and bounds as those devices have been tremendously downsized. As this miniaturization trend accelerates, a contact hole (or a contact formed by filling in the hole with a conductor), provided for interconnecting the gate electrode or doped layer of an MIS semiconductor device to an interconnection layer, has further reduced its size every time size generations alternate.
To reduce a margin needed in overlaying masks one upon the other during a photolithographic process and thereby further increase the number of semiconductor devices integrated, various methods for forming contacts self-aligned with a gate electrode have been researched and developed vigorously. Those contacts will be herein called xe2x80x9cself-aligned contactsxe2x80x9d. Hereinafter, a semiconductor device including the known self-aligned contacts and its fabrication process will be described.
FIG. 22 illustrates a cross section of a known MIS semi-conductor device, including self-aligned contacts, taken in the channel direction (i.e., the gate length direction) thereof. As shown in FIG. 22, a trench isolation film 104 is provided on an Si substrate 101 and an MIS transistor is formed in an active region surrounded by the isolation film 104. The MIS transistor includes: a gate insulating film 105 of SiO2; a gate electrode 106 of polysilicon; an upper insulating film 107 of SiN; a nitride sidewall 109 of SiN; LDD regions 108; and heavily doped source/drain regions 110. The gate insulating film 105, gate electrode 106 and upper insulating film 107 are stacked in this order on the Si substrate 101 and the side faces of the gate electrode 106 and upper insulating film 107 are covered with the nitride sidewall 109. The LDD and heavily doped source/drain regions 108 and 110 are defined in the Si substrate 101 by introducing dopants thereto. Contacts 112 of tungsten, for example, are formed to pass through an interlevel dielectric film 111 over the Si substrate 101 and to reach the heavily doped source/drain regions 110. Depending on the direction of mask misalignment, these contacts 112 come into partial contact with the upper insulating film 107 and nitride sidewall 109. And these contacts 112 are self-aligned contacts that have been automatically aligned with the gate electrode 106.
FIGS. 23A through 23E are cross-sectional views illustrating respective process steps for fabricating the MIS semi-conductor device including the known self-aligned contacts.
First, in the process step shown in FIG. 23A, a stopper insulating film 102, which may be a multilayer structure consisting of silicon dioxide and silicon nitride films, is deposited on an Si substrate 101. Then, parts of the stopper insulating film 102 and Si substrate 101, where the trench isolation will be formed, are etched to a predetermined depth, thereby forming a trench 103 in the Si substrate 101.
Next, in the process step shown in FIG. 23B, a CVD silicon dioxide film is deposited over the substrate and has its surface planarized by a chemical/mechanical polishing (CMP) process using the stopper insulating film 102 as a polish stopper. In this manner, the trench 103 is filled in with the CVD silicon dioxide film, thereby forming the isolation film 104. As a result, the upper surfaces of the isolation film 104 and stopper insulating film 102 are planarized to the same level. Once a desired planarity is attained, the stopper insulating film 102 is removed.
Then, in the process step shown in FIG. 23C, the exposed surface of the Si substrate 101 is thermally oxidized, thereby forming a gate insulating film 105 of SiO2. Subsequently, after polysilicon and silicon nitride film have been stacked in this order over the substrate, these two films are patterned by lithography and dry etching techniques to form a gate electrode 106 and an upper insulating film 107 in the active region. Thereafter, dopant ions are lightly implanted into the Si substrate 101 using the upper insulating film 107 and trench isolation film 104 as a mask, thereby defining LDD regions 108 that are self-aligned with the gate electrode 106.
Next, in the process step shown in FIG. 23D, a silicon nitride film is deposited over the substrate and then etched back, thereby forming a nitride sidewall 109 over the side faces of the upper insulating film 107 and gate electrode 106. Thereafter, dopant ions are heavily implanted into the Si substrate 101 using the upper insulating film 107, nitride sidewall 109 and trench isolation film 104 as a mask, thereby defining heavily doped source/drain regions 110 that are self-aligned with the gate electrode 106.
Subsequently, in the process step shown in FIG. 23E, a relatively thick CVD silicon dioxide film is deposited over the substrate and then planarized by a CMP process, thereby forming an interlevel dielectric film 111. Thereafter, contact holes, reaching the heavily doped source/drain regions 110, are opened through the interlevel dielectric film 111 and filled in with a conductor, thereby obtaining source/drain contacts 112 that make electrical contact with the heavily doped source/drain regions 110.
According to this method, when the contact holes are opened through the interlevel dielectric film 111 so as to reach the heavily doped source/drain regions 110, the gate electrode 106 has already been covered with the SiN upper insulating film 107 and nitride sidewall 109. Thus, even if these contact holes have been formed to overlap with the gate electrode 106 due to mask misalignment, the silicon nitride film 107 serves as an etch stopper. As a result, the source/drain contacts 112 can be formed as self-aligned contacts without making the contact holes partially etch the gate electrode 106.
The semiconductor device including the known self-aligned contacts and its fabrication process, however, has the following drawbacks.
Firstly, according to the known method of making the self-aligned contacts, the source/drain contacts must be formed within the contact holes that have been prepared by lithography and dry etching processes. Thus, the size of the source/drain contacts can be reduced to no smaller than the minimum opening size of a resist pattern for use in an exposure process.
The self-aligning technique for the known self-aligned contacts was developed to form the contact holes, reaching the source/drain regions, without getting the gate electrode etched even if those holes horizontally overlap with the gate electrode due to the placement error of photomasks for use in making the holes. This is because the upper and side faces of the gate electrode have already been covered with the silicon nitride film when those holes are opened. That is to say, this self-aligned contact making method was designed to increase an allowable mask overlay margin for a photolithographic process for forming the contact holes. Thus, the size of the contact holes themselves, in which the contacts should be formed by filling the holes with a conductor, is determined by the minimum opening size of a resist pattern.
FIG. 24A is a cross-sectional view illustrating an MIS transistor including the known self-aligned contacts along with the sizes of respective parts of the transistor. FIG. 24B is a plan view illustrating a photomask used for forming the contact holes.
As shown in FIG. 24A, the contact holes 114 reaching the heavily doped source/drain regions 110 are formed by etching the interlevel dielectric film 111 using a resist pattern 113 as a mask. Thus, it is impossible to reduce the size of the contact holes 114, in which the source/drain contacts should be formed, to less than the minimum opening size of the resist pattern 113 (i.e., a positive photoresist film in the illustrated example). The lower part 114a of the contact hole 114 on the left-hand side, located between the nitride sidewall 109 and interlevel dielectric film 111, has a size smaller than the minimum opening size. However, this part 114a is formed due to the mask misalignment and this size is non-controllable. Accordingly, when a contact is formed inside the contact hole 114, the area of contact between the contact and the heavily doped source/drain region 110 is smaller than the desired one. On the other hand, the upper part 114b of the contact hole 114 has a size approximately equal to the minimum opening size. Thus, it is virtually impossible to reduce the area of contact between the contact formed inside the contact hole 114 and an interconnection line, which will be formed on the contact, to less than the minimum opening size.
According to a normal exposure technique, the gate length determined by a resist pattern for a gate electrode (i.e., the length of the resultant gate electrode 106) may be equal to the minimum opening size (or the design rule in this case), e.g., 0.15 xcexcm. However, the resolution of a resist pattern with no line-and-space pattern, e.g., a resist pattern for making contact holes, is lower than that of a gate electrode pattern. Accordingly, openings with the minimum size of 0.15 xcexcm cannot be formed, and therefore the minimum opening size of the resist pattern 113 shown in FIG. 24A is about 0.2 xcexcm in a normal case. Thus, if the gate length of the gate electrode is defined at the minimum opening size, it is difficult to reduce the size of the source/drain contacts (or contact holes) to approximately equal to, or less than, the gate length in accordance with the currently available technique.
Secondly, the relative positional relationship among the gate electrode, trench isolation film and source/drain contacts is changeable depending on the mask overlay accuracy of an exposure system. Thus, an extra mask overlay margin is needed and the area of the active region cannot be reduced proportionally to a reduced design rule. Accordingly, it is now very difficult to further reduce the areas of the source/drain regions or the coupling capacitance formed between the source/drain regions and the substrate.
Usually, a photomask is designed in such a shape that the contact holes 114 will not overlap with the gate electrode 106 but will be located over the heavily doped source/drain regions 110 as shown in FIG. 24B. Suppose a semiconductor device has been formed by using such a photomask and by setting the mask overlay margin to zero and the gate length of the gate electrode 106 to the minimum opening size. In that case, the sizes of respective parts of the semiconductor device as measured in the channel direction (i.e., the gate length direction) will be as shown in FIG. 24A. The gate length of the gate electrode 106 will be 0.15 xcexcm. The horizontal size of the nitride sidewall 109 will be 0.12 xcexcm in total (i.e., 0.6 xcexcm each side). And the size of part of the source/drain region 110 that is located between the nitride sidewall 109 and trench isolation film 104 as measured in the gate length direction will be 0.4 xcexcm in total (i.e., 0.2 xcexcm each side). As described above, this size is approximately equal to the designed size of the contact holes 114. Add all of these sizes together, and the size of the entire active region interposed between the right- and left-hand side portions of the isolation film 104 will be about 0.67 xcexcm as measured in the gate length direction. The size of the active region except the gate electrode 106 with the length of 0.15 xcexcm will be about 0.52 xcexcm in total (i.e., 0.26 xcexcm each side) as measured in the gate length direction. The size of the heavily doped source/drain regions 110, including their parts diffused under the gate electrode 106, will also be about 0.52 xcexcm in total (i.e., 0.26 xcexcm each side) as measured in the gate length direction. On the other hand, supposing a mask overlay margin of about 0.01 xcexcm is needed in aligning each pair of parts with each other, the size of the entire active region will be about 0.75 xcexcm as measured in the gate length direction. Even if the design rule for a gate electrode, for example, has been reduced, this mask overlay margin does not decrease proportionally. Since it is expected that the design rule will be continuously reduced from now on, the mask overlay margin will constitute an increasingly great obstacle to downsizing of semiconductor devices.
According to the sizes specified above, the sizes of the active region and heavily doped source/drain regions as measured in the gate length direction are five or more times greater and four or more times greater than the gate length, respectively. Thus, it is necessary, but very difficult, to further reduce these sizes of the active region and heavily doped source/drain regions for the purpose of downsizing the semiconductor devices and reducing the junction capacitance.
To further downsize the semiconductor devices, the present invention adopts a completely new approach, which is totally different from the prior art.
An object of this invention is providing a downsized semiconductor device, of which the components can be freely disposed in an active region without being limited by the mask overlay margin, by self-aligning not only the contacts but also the isolation film as well with the gate electrode.
Another object of this invention is providing a method for fabricating the device by this new self-aligning technique.
An inventive semiconductor device includes: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film; an upper insulating film formed on the gate electrode; and a trench isolation film self-aligned with the gate electrode. The upper surface of the isolation film is located at a level higher than the upper surface of the gate electrode. The lower surface of the isolation film is located at a level lower than the upper surface of the substrate at least on a cross section of the device taken in a gate length direction. The device further includes: source/drain diffused regions defined in respective regions of the substrate beside the gate electrode; source/drain contacts formed between the gate electrode and the isolation film and self-aligned with the gate electrode to make electrical contact with the source/drain diffused regions; and a sidewall insulating film interposed between the source/drain contacts and a stack of the gate electrode and the upper insulating film.
In the inventive semiconductor device, the upper surface of the trench isolation film is higher than that of the gate electrode and the source/drain contacts are interposed between the gate electrode and the isolation film. In addition, since the source/drain contacts and the isolation film are both self-aligned with the gate electrode, no mask overlay margin is needed. Accordingly, the active region, surrounded by the isolation film, can have its size reduced in the gate length direction.
In one embodiment of the present invention, as viewed from over the device, the source/drain contacts are preferably in substantially the same planar shape as the source/drain diffused regions in respective areas where the contacts overlap the diffused regions, and are preferably formed only over the diffused regions. Unlike the known source/drain contacts, which are formed by filling in contact holes with a conductor, the contacts can be made in any size. That is to say, the size of the source/drain contacts as measured in the gate length direction can be smaller than the minimum opening size. For example, the size of the source/drain contacts as measured in the gate length direction may be in the range from 0.01 xcexcm to 0.1 xcexcm.
In another embodiment of the present invention, the respective upper surfaces of the upper insulating film, the isolation film and the source/drain contacts are preferably planarized to substantially the same levels. In that case, the planarity of the substrate increases as a whole, thus improving the reliability of upper-level interconnects, for example.
In still another embodiment, on a transversal cross section of the device taken across a part of the gate electrode, a periphery, outlining the sidewall insulating film, the gate electrode and the source/drain contacts, is preferably surrounded by the isolation film. Then, the isolation capability of the semiconductor device improves.
In yet another embodiment, the gate electrode in its entirety is preferably located only over the gate insulating film.
In still another embodiment, on a transversal cross section of the device taken across a part of the gate electrode, a trench may be provided in the substrate around a periphery outlining the sidewall insulating film, the gate electrode and the source/drain contacts, and filled in with the isolation film.
In still another embodiment, on a cross section of the device taken in a gate width direction, the isolation film may be formed only over the upper surface of the substrate. And the device may further include a gate-width-defining trench isolation film, which reaches at least a region under a portion of the gate electrode where a contact will be formed on the cross section taken in the gate width direction. In such an embodiment, the channel region is sandwiched by the gate-width-defining trench isolation film, thus reducing the variation in electrical characteristics of the semiconductor device.
An inventive method for fabricating a semiconductor device includes the steps of: a) forming a first insulating film, a conductor film and a second insulating film in this order over a semiconductor substrate, where the first insulating film and the conductor film will be shaped into a gate insulating film and a gate electrode, respectively; b) forming an upper insulating film and the gate electrode by patterning at least the second insulating film and the conductor film, respectively; c) forming a self-aligned sidewall film on the side faces of the gate electrode so that the sidewall film is self-aligned with the gate electrode; and d) etching the substrate to a predetermined depth using the upper insulating film and the self-aligned sidewall film as a mask, thereby forming a trench self-aligned with the gate electrode.
According to the inventive method, the trench can be formed to be self-aligned with the gate electrode. Thus, the size of the regions interposed between the gate electrode and the trench can be reduced in the gate length direction.
In one embodiment of the present invention, two types of selectively etchable insulating films may be stacked one upon the other in the step a) as the second insulating film. And in the step b), a stack of first and second upper insulating films may be formed as the upper insulating film. In such an embodiment, the substrate can be planarized more easily after that.
In another embodiment of the present invention, the method may further include the steps of: e) forming a third insulating film over the substrate after the step d) has been performed; and f) removing part of the third insulating film at least until the surfaces of the upper insulating film and the self-aligned sidewall film are exposed, thereby forming a trench isolation film that extends from the bottom of the trench and reaches a level at least higher than the upper surface of the gate electrode. In this manner, the isolation film can be formed to be self-aligned with the gate electrode.
In this particular embodiment, the respective upper surfaces of the upper insulating film, the self-aligned sidewall film and the isolation film are preferably planarized in the step f) to substantially the same levels by a CMP process.
In an alternative embodiment, two types of selectively etchable insulating films may be stacked one upon the other in the step a) as the second insulating film. In the step b), a stack of first and second upper insulating films may be formed as the upper insulating film. And in the step f), parts of the third insulating film, the second upper insulating film and the self-aligned sidewall film may be removed until the surface of the first upper insulating film is exposed. A self-aligned sidewall film of a good shape can be obtained by doing so. Accordingly, whether this self-aligned sidewall film is used as the source/drain contacts themselves or their dummies, the reliability of the resultant semiconductor device improves.
In this particular embodiment, the respective upper surfaces of the first upper insulating film, the self-aligned sidewall film and the isolation film are preferably planarized in the step f) to substantially the same levels by a CMP process.
In still another embodiment, the method may further include the steps of: g) selectively removing the self-aligned sidewall film after the step f) has been performed, thereby forming contact holes reaching the substrate; h) filling the contact holes with a conductor, thereby forming source/drain contacts that reach source/drain diffused regions and are self-aligned with the gate electrode; i) introducing a dopant into respective regions of the substrate beside the gate electrode to define the source/drain diffused regions self-aligned with the gate electrode; and j) forming a sidewall insulating film between the source/drain contacts and the stack of the gate electrode and the upper insulating film. The step i) may be performed after the step b) has been performed, while the step j) may be performed at any point between the steps b) and h). In such an embodiment, respective parts of the semiconductor device can be self-aligned with the gate electrode. Thus, the device can be downsized much more easily.
In this particular embodiment, the step j) may be performed after the step b) so that the sidewall insulating film is left on the side faces of the upper insulating film and the gate electrode.
In this case, the step i) may include the sub-steps of: i-1) defining lightly doped source/drain regions in the substrate by implanting dopant ions lightly into the substrate using the gate electrode as a mask; and i-2) defining heavily doped source/drain regions in the substrate by implanting the dopant ions heavily into the substrate using the gate electrode and the sidewall insulating film as a mask. The step i-1) is preferably performed between the steps b) and j), while the step i-2) is preferably performed after the step j). In this manner, an MIS transistor with a so-called LDD structure can be formed easily with its short channel effect preventing function much improved.
In still another embodiment, the step i) may be performed as an ion implantation process using at least the gate electrode and the isolation film as a mask between the steps g) and h).
In yet another embodiment, the source/drain contacts containing a dopant may be formed in the step h), and the step i) may be performed by diffusing the dopant from the source/drain contacts into the substrate after the step h) has been performed. In such an embodiment, the source/drain regions with a shallow diffusion depth can be formed.
In yet another embodiment, the method may further include the steps of: g) defining source/drain diffused regions in respective regions of the substrate beside the gate electrode between the steps b) and c); and h) forming a sidewall insulating film on the side faces of the upper insulating film and the gate electrode between the steps b) and c). In the step c), a conductor film, which will be source/drain contacts, may be formed as the self-aligned sidewall film on the sidewall insulating film. In such an embodiment, there is no need to perform the steps of forming contact holes by partially removing the self-aligned sidewall film and filling the contact holes with a conductor film, thus simplifying the fabrication process.
In still another embodiment, the method may further include the step of forming a gate-width-defining trench isolation film in the substrate before the step a) is performed. In such an embodiment, the variation in electrical characteristics of the semiconductor device can be suppressed.